1. Field of the Invention
The present invention relates to a liquid crystal display device and a method of fabrication thereof. More particularly, the present invention relates to a liquid crystal display device and a method of fabrication thereof that simplify a fabrication process of the LCD and improve contact resistance properties.
2. Discussion of the Related Art
As modern society moves to an information-oriented society, flat panel displays including liquid crystal display devices (hereinafter, referred to as LCDs) have become more important. The cathode ray tubes (hereinafter, referred to as CRTs) that have been most widely used until now have many advantages in performance and price, but they also have many disadvantages in miniaturization and portability. Compared with the CRTs, LCDs are more expensive, but they have such advantages as miniaturization, lightweight, slimness, and low-power consumption. Due to such advantages, LCDs have drawn public attention as a substitute for the CRTs.
An LCD according to a related art includes an array substrate on which thin film transistors are arranged, a color filter substrate on which red, green, blue color filter layers are formed and which is attached to the array substrate, and a liquid crystal interposed therebetween. The array substrate further includes a transparent glass substrate, gate lines on the transparent glass substrate and data lines crossing the gate lines perpendicularly. Driving signals are supplied through the gate lines, and image signals are supplied through the data lines. The gate lines and the data lines define pixel areas. A thin film transistor (hereinafter, referred to as TFT) as a switching device and a pixel electrode are provided on each of the pixel areas. Pad areas are formed on edge areas of the gate lines and the data lines to provide input signals to the gate and data lines. The driving and image signals generated by printed circuit boards are applied to the pixel areas formed in a matrix configuration through the pad areas. In order to form such elements on the array substrate, metal layers are deposited and etched on the array substrate, or semiconductor materials are sequentially formed and etched on the array substrate.
In the related art, the gate and data lines are formed of metal. In order to improve adhesiveness to other layers or to enhance etching properties, these lines may be formed to have a double-layer structure or a triple-layer structure.
FIGS. 1A through 1F are cross-sectional views of a TFT region, a storage capacitor region, a gate pad region and a data pad region of an array substrate, illustrating a method of fabricating an LCD according to the related art.
Referring to FIG. 1A, AlNd and molybdenum (Mo) layers are sequentially deposited on a glass substrate 10. A wet-etching process and a dry-etching process are performed to form a gate line (not shown), a gate electrode 1, a common line 11 for a storage capacitor, and a gate pad 21 at once. The gate line (not shown), the gate electrode 1, the common line 11 and the gate pad 21 have a double-layer structure composed of AlNd metal layers 1b, 11b and 21b and molybdenum (Mo) metal layers 1a, 11a and 21a. A photolithography process is generally used to form such patterns, which includes coating a photo-resist, exposing and developing the photo-resist, etching a layer using the developed photo-resist as a mask, and then stripping the photo-resist.
Next, as shown in FIG. 1B, a gate insulating layer 3 is formed on the entire area of the glass substrate 10.
Next, as shown in FIG. 1C, an amorphous silicon layer and a doped amorphous silicon layer are sequentially formed on the entire area of the substrate 10 on which the gate insulating layer 3 is formed. Then, the amorphous silicon layer and the doped amorphous silicon layer are etched to form an active layer 5 on the region in which a TFT will be formed. The active layer 5 is also formed on the region in which a storage capacitor will be formed. The storage capacitor will have a predetermined capacitance between the common line 11 and a storage electrode that will be formed later.
Next, as shown in FIG. 1D, a source/drain metal layer is formed on the substrate 10 on which the active layer 5 is formed. Then, the source/drain metal layer is etched to form a source electrode 7a and a drain electrode 7b of the TFT, a storage electrode 17 of the storage capacitor, a data line (not shown) and a data pad 37. The source/drain metal layer has a triple-layer structure in which an AlNd layer is interposed between two chromium (Cr) layers. Accordingly, the source/drain metal layer having a triple-layer structure is dry-etched three times to form the source electrode 7a, the drain electrode 7b, the storage electrode 17 and the data pad 37.
Next, as shown in FIG. 1E, a passivation layer 9 is formed on the substrate 10 on which the source electrode 7a, the drain electrode 7b, the storage electrode 17 and the data pad 37 are formed, and then the passivation layer 9 is etched to form contact holes. The contact holes are formed by etching the passivation layer on the drain electrode 7b, the storage electrode 17 and the data pad 37. The contact hole on the gate pad 21 exposes the gate pad 21 by etching the gate insulating layer 3 and the passivation layer 9.
After forming the contact holes, as shown in FIG. 1F, a conductive layer is deposited on the entire area of the substrate 10 on which the source electrode 7a and the drain electrode 7b are formed, and then the conductive layer is etched to form a pixel electrode 15. The conductive layer is formed of ITO, IZO, ITZO, or the like.
The pixel electrode 15 is electrically connected to the drain electrode 7b through the contact hole formed within the drain electrode 7b. Contact pads 19, 22 and 31 formed of the conductive layer are formed on the areas where the passivation layer 9 of the storage electrode 17, the gate pad 21 and the data pad 37 are removed. In this way, the contact pads 19, 22 and 31 are electrically connected to the storage electrode 17, the gate pad 21 and the data pad 37, respectively.
As described above, the LCD device according to the related art includes the gate lines having a double-layer structure (Mo/AlNd) and the data lines having a triple-layer structure (Cr/AlNd/Cr). Accordingly, multiple etching processes should be sequentially performed to form the gate and data lines, which complicates the fabrication process and increases production cost. In particular, as the panel size of LCD devices becomes large recently due to the demand, the problems described above become more serious. In addition, the contact resistance between the pixel electrode formed of ITO and the drain electrode having a triple-layer structure is large.